The present invention relates generally to resistive loads formed in semiconductor devices, and more particularly, to resistive load structures used in memory cells.
In the semiconductor industry, there is a general need to make semiconductor devices physically smaller, faster, and less expensive to manufacture. In response to this need, semiconductor manufactures have made numerous improvements through the use of more efficient routing arrangements, better performing materials and improved packaging structures.
As is well known in the art, semiconductor memory devices are typically manufactured in large arrays. By way of example, a static random access memory (SRAM) is one type of memory device generally having an array of 2.sup.n by 2.sup.m individual SRAM cells. In turn, each SRAM cell is coupled to wordlines (rows), and complementary bit lines (columns) to enable appropriate programming.
Although there has been much research and development associated with producing high performance SRAM memory cells, the basic SRAM cell design has essentially remained unchanged. Consequently, as more individual SRAM cells are packed onto a silicon chip to form a more dense SRAM array, the overall physical size of the array continues to increase. When this happens, the large physical size of the SRAM array will prevent its implementation in designs having strict size constraints. Therefore, designers who need a lot of memory for their electronic equipment may be forced to enlarge the size of their products in order to accommodate larger memory cell designs.
Generally, there are a variety of circuit layouts suitable for designing SRAM cells. Standard SRAM cell designs have two cross-coupled inverters, including two p-type transistors ("pull-up devices"), two n-type transistors ("pull-down devices"), and two pass transistors for a total of six transistors. As a result, some space conscience designers have replaced the two p-type transistors with polysilicon resistors, reducing the transistor count to four. In operation, the two p-type transistors (of the standard design) or the polysilicon resistors (of the modified design) act as a load (pull-up devices) to counteract charge leakage at the drains of the two n-type transistors and the two pass transistors.
FIG. 1 is a circuit diagram of a prior art high resistance SRAM cell 100 having a pair of n-type transistors 106 and 104. Transistors 106 and 104 have gates that are connected to nodes 109 and 107, respectively. A load resistor 110, connects node 109 to a power supply (Vdd) 101 through a power supply node 103. A load resistor 108 connects node 107 to power supply 101. A pass transistor 114 connects node 109 to a data line 118. A pass transistor 112 connects node 107 to a complementary data line 116. The gates of each pass transistor 114 and 112 are connected to a wordline 120, and each of the transistors 104 and 106 are connected to ground (Vss) 102.
Although the substitution of polysilicon load resistors 108 and 110 for the p-type transistors of traditional prior art SRAM cells has somewhat reduced the physical size of an SRAM cell, additional process fabrication operations are typically required to manufacture the polysilicon resistor structures. Additionally, the resistive values of a polysilicon resistor structures are directly related to the length and width of the polysilicon material. Consequently, the use of polysilicon resistor structures may actually increase the silicon surface area required for an SRAM cell.
FIG. 2 is a cross-sectional view of a portion of an integrated circuit embodying the schematic design of the prior art high resistance SRAM cell 100 of FIG. 1. This cross-section illustrates the increased number of process operations required to layout SRAM cell 100 having a polysilicon resistor 108. As shown, a substrate 130 (such as a silicon wafer) is provided with a pair of field oxide (SiO.sub.2) regions 132 and a gate oxide 134. Gate oxide 134 is thermally grown and patterned over substrate 130 and portions of the pair of field oxide regions 132. A polysilicon gate 106 is deposited over gate oxide 134, such as by using conventional chemical vapor deposition (CVD) techniques, and is then patterned. Once patterned, a layer of oxide or nitride is blanket deposited and etched back to form spacers 135.
Next, a dielectric layer 136 of silicon dioxide (SiO.sub.2) is blanket deposited over polysilicon gate 106 and spacers 135, such as by using conventional TEOS deposition techniques. Next, a contact hole 137 is formed in dielectric layer 136 so that a layer of polysilicon material 138 that is subsequently deposited over dielectric layer 136 comes in contact with polysilicon gate 106. Typically, an implant operation follows where polysilicon material 138 is doped with impurities such as phosphorous and arsenic. Once polysilicon material 138 is patterned, a dielectric layer 140 is blanket deposited over polysilicon material 138 and other exposed areas. Next, a conductive contact 144 is formed in dielectric layer 140, which leads to a patterned metallization line 146.
The resulting structure includes a polysilicon resistor 108 formed of polysilicon material 138. As described above, the resistance of polysilicon resistor 108 is partially controlled by the physical width (W) of polysilicon material 138, since the current flows along the width of the resistor. Consequently, as increased resistive loads are needed, the width W must increase, and therefore, the physical size of SRAM cell 100 will unfortunately increase in order to accommodate wider polysilicon material 138 lines. Further, as can be appreciated from the above described process operations, forming polysilicon resistor 108 over gate 106 requires numerous time consuming and complex processing operations in order to achieve the required level of resistance for SRAM cell 100.
In view of the foregoing, what is needed is a resistive load structure and method for making the load structure which conserves space and requires fewer processing operations. Preferably, the needed resistive load structure can be implemented in an SRAM memory device in order to achieve a more compact memory cell.